Technical Document "Clock Domain Crossing in the FPGA World"
To achieve a design that is not affected by metastability.
Clock Domain Crossing (CDC) issues are causing significant failures in ASIC and FPGA devices. As the complexity and performance of FPGAs increase, the impact of CDC issues on design functionality becomes even greater. This paper discusses CDC issues and solutions for FPGA design. It presents various design techniques along with examples from Xilinx and Intel FPGA devices. More importantly, this paper summarizes the most critical CDC guidelines for reliable FPGA design.
- Company：アルデック・ジャパン
- Price：Other
